Memory circuits are well known, and include an array of memory cells, each capable of storing a bit of information. In order to appropriately access a desired word of information, comprising a plurality of bits, appropriate row decoder circuits are used which select appropriate row lines (or word lines) for access. Similarly, column accessing circuitry is often employed to select an appropriate number of bits within the row for output.
FIG. 1 is a block diagram of a typical flash memory device 100 including a memory cell array 120 having a plurality of memory cells such as flash EEPROM cells, which have the same structure as depicted in FIG. 2 to be described below. The memory cell array 120 is divided into a plurality of sectors (or blocks) 125 each of which is a basic erase unit. Each of the sectors 125 is composed of a plurality of segments 126 having a plurality of word lines (for example, eight word lines), a plurality of bit lines arranged so as to intersect the word lines, and a plurality of memory cells connected to the word lines and the bit lines. A address circuit 160 applies row information to a row decoder circuit 140 defining which of the word lines (or rows) of the memory cell array 120 is to be selected for reading or writing. The row decoder circuit 140 is composed of a plurality of segment decoders 151, each of which corresponds to the segments, respectively. Each of the segments 126 in a selected sector 125 (or block) will be selected by the corresponding segment decoder 151 in accordance with a segment select information, one of the word lines in the selected segment 126 will be selected thereby in accordance with a word line select information. Similarly, a column decoder circuit 180 receives address information defining which one or ones of the bit lines (or columns) of the memory cell array 120 are to be selected. Data read from or to be applied to the memory cell array 120 is stored in data buffer circuit 200.
Referring to FIG. 2, there is illustrated a block configuration diagram of the segment decoder 151 in FIG. 1. The segment decoder 151 is composed of a segment selector 141 and a plurality of word line drivers 150 connected to corresponding word lines WL1 to WLn in a segment 126, respectively. When one segment is selected by the segment selector 141 and one of word line select signals S1 to Sn is enabled, one of the word lines WL1 to WLn in the selected segment is selected and driven by corresponding word line driver 150 receiving the enabled word line select signal.
FIG. 3 shows a part of memory cell array 120 in FIG. 1 and a detailed circuit diagram of a segment selector 141 and a word line driver 150. For the sake of simplicity, the row decoder 140 according to the prior art shown in FIG. 2 will be discussed in connection with one word line, and it is to be understood that like circuits are coupled to each word line. In FIG. 3, memory cells 121, which can be flash EEPROM cells (or referred to as ETOX-type cells) are arranged in matrix form. Word lines 122 are commonly connected to gates (or control gates) of the memory cells 121 arranged in the same row of the memory cell array 120. Bit lines 123 are arranged so as to intersect the word lines 122 and commonly connected to drain regions of the memory cells 121 arranged in the same column of the memory cell array 120.
In the memory cell array 120, during the read mode of operation, a voltage (for example, 4.5V) is applied to a selected word line 122, and an intermediate voltage (for example, 1V) is applied to a selected bit line 123. During a write (or programming) mode of operation, a high voltage (for example, 10V) is applied to the selected word line 122, and a high voltage (for example, 5V) is also applied to the selected bit line 123. During an erase mode of operation, the bit lines 123 and the source lines 124 all become a floating state, and a negative voltage (for example, -10V) is also applied to all the word lines 122.
As illustrated in FIG. 3, the segment selector 141 comprises an NAND gate G1 and an NMOS transistor 142. The NAND gate G1 receives and decodes segment select signals Pi and Qi. The NMOS transistor 142 is connected to the output of the NAND gate G1 and a word line driver 150, and has its gate connected to a Shut-Off voltage. The word line driver 150 is connected to a first power node 151, a second power node 152, and a corresponding word line 122, and applies a first voltage VPX supplied to the first power node 151 to the word line 122 during the read and write modes of operation in response to a corresponding word line select signal Si. The word line driver 150 applies a second voltage VEX supplied to the second power node 152 to the word line 122 during the erase mode of operation in response to the word line select signal Si.
The word line driver 150 is comprised of two NMOS transistors 143 and 147 and three PMOS transistors 144, 145 and 146. The NMOS transistor 143 whose gate is connected to the word line select signal Si line 148 has a current path formed between a node ND and the segment selector 141. The PMOS transistor 144 whose current path is formed between the first power node 151 and the node ND has its gate connected to the word line select signal Si line 148. The PMOS transistor 145 whose gate is connected to the word line 122 has its current path formed between the node VPX and ND. The PMOS transistor 146 has its gate connected to the node ND and its current path formed between the first power node 151 and the word line 122. A gate of the NMOS transistor 147, connected to the node ND, has a current path formed between the word line 122 (that is, the PMOS transistor 146) and the second power node 152. The transistors 146 and 147 serve as a CMOS inverter circuit (or pull-up and pull-down transistors).
The first power node 151 is provided as the first voltage VPX with a voltage of approximately 4.5V and a voltage of about 10V during the read and programming modes of i operation, respectively. The second power node 152 receives a ground voltage 0V during the read and programming modes of operation, and receives a voltage of approximately -10V during an erase mode of operation. Thus, the word line driver 150 acts as a voltage level shifter of a shift-up type for transferring the several voltages into the word line 122.
The operation of the memory cell array 120 of FIG. 3 will be explained. Assuming that one of the sectors 125 of the memory cell array 120 is selected for the sake of simplicity, it is readily apparent to those skilled in the art that other sectors 125 can be operated by the same manner as described below.
During the read mode of operation, segment select signals Pi and Qi applied into the NAND gate G1 corresponding to a segment to be selected are at high level (for example, a power supply voltage), and the word line select signal Si corresponding to a word line to be selected in the selected segment is at the high level, a first and second voltages VPX and VEX are 4.5V and 0V, respectively. At this time, outputs of the respective NAND gates G1 in segment selectors 141 corresponding to unselected segments 126 are at the high level, word line select signals Si corresponding to unselected word lines in the selected segment 126 and unselected segments 126 are at the low level, and the first voltage VPX of 4.5V and the second voltage VEX of 0V are commonly applied to the unselected segments 126. Under this condition, the transistors 143 and 146 in the word line driver 150 corresponding to the selected word line 122 will be conductive, enabling the selected word line 122 to be pulled up to the first voltage VPX of 4.5V through the turned-on PMOS transistor 146. On the contrary, the unselected word lines associated with the selected segment 126 and the unselected segments 126 are at the second voltage VEX of 0V because the transistors 143 and 146 therein will be non-conductive and the transistors 144,145 and 146 therein will be conductive.
During the write mode of operation, the output of the NAND gate G1 corresponding to the selected segments 126 is at the low level, the word line select signal Si corresponding to the selected word line 122 is at the high level, and the first and second voltage VPX and VEX are 10V and 0V, respectively. At the same time, the outputs of the respective NAND gates G1 corresponding to the unselected segments 126 are at the high level, the word line select signals Si corresponding to the unselected word lines 122 are at the low level, and the first voltage VPX of 10V and the second voltage VEX of 0V are commonly applied to the unselected segments.
According to this bias condition, the transistors 143 and 146 in the word line driver 150 corresponding to the selected word line 122 will be conductive, enabling the selected word line 122 to be pull up to the first voltage VPX of 10V through the turned-on PMOS transistor 146. On the contrary, the unselected word lines are at the second voltage VEX of 0V because the transistors 143 and 146 therein will be non-conductive and the transistor 144, 145, and 146 therein will be conductive.
During the erase mode of operation, outputs of the NAND gates G1 corresponding to all the segments 126 (that is, in one sector 125 being an erase unit) are at low level, word line select signals Si respectively corresponding to the word lines in each segment 126 are at high level, and the first voltage VPX and the second voltage VEX are 0V and -10V, respectively.
Note that the Shut-off voltage is 0 V during the erase mode of operation. Under this bias condition, the transistors 144 and 147 will be conductive, causing all the word lines 122 of the selected sector 125 to be pull down to the second voltage VEX of approximately -10V. At this time, the transistors 144, 145, and 146 will be turned off.
A test mode operation is commonly performed for detecting each threshold voltage distribution of flash EEPROM cells in the memory cell array 120. During the test mode of operation, in order to detect a memory cell state, a voltage on a selected word line may be changed sequentially from the lowest voltage level (for example, 1V indicating an over-erase verification level) to the highest voltage level (for example, 6V indicating a programming verification level). The operation of the word line driver 150 in FIG. 3 during the test mode of operation differs from that of the read mode of operation only in that the first voltage VPX is changed instead of being maintained at a fixed voltage during the test mode of operation. In the row decoder 140 (FIG. 1) according to the above-mentioned prior art, there is a problem to be described below when the test mode of operation is performed.
In the word line drivers 150 associated with both an unselected segment and the word line select signal Si being at the low level during the test mode of operation, the node ND thereof is at the high level (for example, 4V), the word line select signal Si is at low level (for example, 0V), and the second voltage VEX is 0V. According to this bias condition, if the first voltage VPX is varied from 1V to 4V, the first power node 151 and the node ND are momentarily shorted electrically through the PMOS transistor 144. That is, as shown in FIG. 4, a forward bias condition is formed between the node ND and the bulk of the PMOS transistor 144, and also the PMOS transistor 144 is somewhat conductive. This raises the first voltage VPX while the test operation is being performed. Therefore, it is impossible to perform a test operation by use of the row decoder circuit 140 when the first voltage VPX is less than the high level of the power supply voltage.